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Live Course

VLSI Physical Design Training

4.6(95 ratings)
VLSI Physical Design হচ্ছে semiconductor chip development এর একটি গুরুত্বপূর্ণ পর্যায়, যেখানে লজিক্যাল সার্কিটকে রূপান্তর করা হয় বাস্তব সিলিকন লেআউট-এ। এই ধাপ সম্পন্ন হওয়ার পরই একটি design manufacturing এর জন্য প্রস্তুত হয়ে ওঠে। এই কোর্সে আপনি Physical Design (PD) এর মৌলিক ধারণা থেকে শুরু করে প্রতিটি ধাপ যেমন Floorplanning, Placement, Routing, Clock Tree Synthesis (CTS), Power Planning, Physical Verification, Timing Closure সহ অন্যান্য প্রয়োজনীয় বিষয় অত্যন্ত সহজবোধ্য উপায়ে শিখবেন। শেখার সম্পূর্ণ প্রক্রিয়াটি সাজানো হয়েছে বাস্তব উদাহরণ, industry-grade open-source tools (OpenROAD) এবং হাতে-কলমে প্র্যাকটিসের মাধ্যমে, যাতে আপনি খুব সহজেই industry ready skills অর্জন করতে পারেন এবং আত্মবিশ্বাসের সাথে VLSI industry তে ক্যারিয়ার গড়ে তুলতে পারেন।
11
Modules
22
Live Classes
1
Projects
Batch Number
1
Start Date
January 15
Class Days
Wed, Sat
Class Time
9:30 - 11:00 PM
VLSI Physical Design Training
Watch Course Demo
৳18,000৳30,000
40% OFF

Course Module

Module
1

PD Prerequisites

6 Live Classes
Module
2

Introduction to Physical Design

1 Live Class
Module
3

Floorplanning

1 Live Class
Module
4

PowerPlanning

1 Live Class
Module
5

Placement

2 Live Classes
Module
6

Clock Tree Synthesis (CTS)

2 Live Classes
Module
7

Routing

2 Live Classes
Module
8

Timing Analysis & Optimization

2 Live Classes
Module
9

Signoff & Verification

2 Live Classes
Module
10

Capstone Project

3 Live Classes
Module
11

Job Exam & Interview Preparation

2 Live Classes

What You will Get in This Course

Complete Understanding of ASIC Design Flow

Complete Understanding of ASIC Design Flow

Learn the entire process from RTL to GDSII with practical insights.

Solid Foundation in Physical Design (PD)

Solid Foundation in Physical Design (PD)

Master every PD stage: Floorplanning, Placement, CTS, Routing, and Sign-off.

Hands-on Practice with EDA Tools

Hands-on Practice with EDA Tools

Get real-world experience using OpenROAD and other open-source design tools.

Expertise in Timing, Power, and Area Optimization

Expertise in Timing, Power, and Area Optimization

Learn how to achieve efficient chip performance through key optimization techniques.

Experience with Open-Source PDKs

Experience with Open-Source PDKs

Work with SkyWater 130nm and similar open-source fabrication technologies.

Unlimited Live Support

Unlimited Live Support

Get instant help and guidance whenever you need it throughout the course.

Completion Certificate

Completion Certificate

Earn a verified certificate to enhance your resume and LinkedIn profile.

Guidance for Interviews & Career Growth

Guidance for Interviews & Career Growth

Receive expert tips and mock interview support for semiconductor job preparation.

Confidence to Work on Real ASIC Design Teams

Confidence to Work on Real ASIC Design Teams

Be fully equipped to contribute to industry or research-level chip design projects.

Projects You Will Build

Project 1

RTL to GDSII SoC Project – Take a Verilog RTL, synthesize, floorplan, place, route, and generate GDSII.

RTL to GDSII SoC Project – Take a Verilog RTL, synthesize, floorplan, place, route, and generate GDSII.
Project 2

Open-Source Tapeout Simulation – Use OpenLANE & SkyWater PDK to generate a complete tapeout-ready GDSII.

Open-Source Tapeout Simulation – Use OpenLANE & SkyWater PDK to generate a complete tapeout-ready GDSII.

Who This Course is For

Undergraduate/Graduate Students – Interested in VLSI & semiconductor design.

Undergraduate/Graduate Students – Interested in VLSI & semiconductor design.

Fresh Engineers – Preparing for jobs in ASIC/SoC companies.

Fresh Engineers – Preparing for jobs in ASIC/SoC companies.

Researchers & Enthusiasts – Exploring EDA, CAD, and chip layout methodologies.

Researchers & Enthusiasts – Exploring EDA, CAD, and chip layout methodologies.

Professionals – Who want to skill up in physical design for better career opportunities.

Professionals – Who want to skill up in physical design for better career opportunities.

What You will Need to Get Started

1
Laptop/Workstation: Minimum 8GB RAM (16GB+ recommended for EDA tools)

Laptop/Workstation: Minimum 8GB RAM (16GB+ recommended for EDA tools)

2
Operating System: Linux (Ubuntu/CentOS)

Operating System: Linux (Ubuntu/CentOS)

3
Background Knowledge: Basics of Digital Logic Design and Electronics

Background Knowledge: Basics of Digital Logic Design and Electronics

4
Mindset: Patience + Practice (Physical design requires iterative debugging

Mindset: Patience + Practice (Physical design requires iterative debugging

Instructors and Mentors

Arnob Karmokar

Arnob Karmokar

ASIC PD Engineer

PrimeSilicon Technology BD Ltd

A.B.M Tafsirul Islam

A.B.M Tafsirul Islam

Physical Design Engineer

Neural Semiconductor Ltd

Ashikur Rahman

Ashikur Rahman

Senior SOC Engineer

Intel

Frequently Asked Questions (FAQ)

৳18,000৳30,000
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